1. Technical Field
Embodiments of the present invention described herein relate to a semiconductor circuit technology, and in particular, to a sense amplifier and a semiconductor integrated circuit using the same.
2. Related Art
A semiconductor integrated circuit 10 according to the conventional art includes a bit line ‘BL’, a /bit line ‘BLB’, a word line ‘WL’, a memory cell 11, a sense amplifier 12, and precharge circuits 13 and 14, as shown in FIG. 1.
The sense amplifier 12, which is a component for sensing and amplifying data recorded in the memory cell 11, is electrically connected between the bit line ‘BL’ and the /bit line ‘BLB’ and includes a plurality of transistors ‘M1 to M6’.
The sense amplifier 12, which is in a cross coupled latch form, includes inverter pairs that are configured of transistors M1 and M2 and transistors M3 and M4.
The transistor ‘M5’ is electrically connected between the cross coupled latch and a power supply terminal ‘VCORE’. A gate of the transistor ‘M5’ receives a control signal ‘SAP’. The transistor ‘M6’ is electrically connected between the cross coupled latch and a ground terminal ‘VSS’. A gate of the transistor ‘M6’ receives a control signal ‘SAN’. The control signals ‘SAP and SAN’ are signals that determine a timing supplying power to the sense amplifier 12.
The precharge circuits 13 and 14 precharge the bit line pairs to a bit line precharge voltage ‘VBLP’ level according to a bit line equalize signal ‘BLEQ’. The precharge circuits 13 and 14 may be configured of a plurality of transistors ‘M7 to M12’.
At this time, a mismatch between the transistors that configure the inverter pairs of the sense amplifier 12 may occur due to a problem of the elements or processes. An offset between the transistors forming the inverter pair, that is, a difference in a threshold voltage that is different from a circuit design may occur due to the mismatch.
In addition, since the transistors ‘M5 and M6’ and the transistors ‘M7 to M12’ configuring the precharge circuits 13 and 14 are a component that has a connection with a power supply, they are designed at a larger size than the transistors ‘M1 to M4’ configuring the inverter pairs of the sense amplifier 12.
The semiconductor integrated circuit according to the conventional art, which is configured as described above, precharges the bit line ‘BL’ and the /bit line ‘BLB’ at the bit line precharge voltage ‘VBLP’ level by the precharge circuits 13 and 14 before the word line ‘WL’ is activated.
Thereafter, as the word line ‘WL’ is activated for read or refresh operations, the charge sharing of the bit line ‘BL’ and the /bit line ‘BLB’ is made.
After a time elapses by a degree that the voltage difference of the bit line ‘BL’ and the /bit line ‘BLB’ is the desired level or more by the charge sharing, the control signals ‘SAP and SAN’ are activated.
The sense amplifier 12 is operated according to the activation of the control signals SAP and SAN, such that the sensing and amplifying operations of data recorded in the memory cell 1 can be made.
The semiconductor integrated circuit according to the above-mentioned conventional art has the following problems.
First, the bit line ‘BL’ and the /bit line ‘BLB’ are precharged at the same voltage level, that is, the bit line precharge voltage ‘VBLP’ level. However, the sense amplifier does not reflect the voltage difference of the bit line ‘BL’ and the /bit line ‘BLB’ due to the offset of the inverter pairs and thus, a malfunction may occur.
For example, it is assumed that “1” is recorded in the memory cell 11. When the word line ‘WL’ is activated, the voltage level of the bit line ‘BL’ is higher than the bit line precharge voltage ‘VBLP’ and the voltage level of the /bit line ‘BLB’ will maintain the bit line precharge voltage ‘VBLP’. At this time, if it is assumed that the threshold voltage of the transistor ‘M2’ is in a lower state than that of the design and the threshold voltage of the transistor ‘M4’ is in a higher state than that of the design, the voltage of the bit line ‘BL’ is discharged through the transistor ‘M6’ by the transistor ‘M2’ such that the data of the memory cell 11 is wrongly sensed as “0”.
Second, since the transistors ‘M5 and M6’ for supplying power and the transistors ‘M7 to M12’ for the precharge operation are needed, the reduction in the circuit area to form the transistors occurs.